1. Technical Field
This invention relates to computing systems, and more particularly, to techniques for handling hardware and software interrupts in the system.
2. Description of the Related Art
Computer systems may include multiple processors or nodes, each of which may include multiple processing cores. Such systems may also include various Input/Output (I/O) devices, which each processor may send data to or receive data from. For example, I/O devices may include ethernet network interface cards (NICs) that allow the processors to communicate with other computer systems, and external peripherals such as printers, for example. Various forms of storage devices, such as, e.g., mechanical and solid-state disk drives, and the like, may also be included with a computing system.
I/O devices, such as those described above, may send interrupts to signal various events. For example, an I/O device may send an interrupt to signal the completion of a direct memory access (DMA) operation. An I/O device may also be sent to inform software of an internally detected error, or of an error on an I/O link coupled to the I/O device.
Each processor may have multiple threads of execution. When an interrupt is received, a designated processing thread may execute specialized program instructions. Such program instructions may include instructions to query and/or clear error status or log registers. Dependent upon the severity of the error that initiated the interrupt, portions of the computer system may be reset, or hardware may be reconfigured.